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?2001 silicon storage technology, inc. 327-3 2/01 s71065 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. flashbank is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet 16 megabit flashbank memory sst38vf166 features: ? single 2.7-3.6v read and write operations separate memory banks for code or data ? simultaneous read and write capability superior reliability ? endurance: e 2 bank - 500,000 cycles (typical) flash bank - 100,000 cycles (typical) ? greater than 100 years data retention low power consumption ? active current, read: 15 ma (typical) ? active current, concurrent read while write: 40 ma (typical) ? standby current: 3 a (typical) ? auto low power mode current: 3 a (typical) fast write operation ? flash bank-erase + program: 8 sec (typical) ? flash block-erase + program: 500 ms (typical) ? flash sector-erase + program: 30 ms (typical) ? e 2 bank word-write: 9 ms (typical) fixed erase, program, write times ? remain constant after cycling read access time ? 70 ns latched address and data end-of-write detection ? to g g l e b i t ? data# polling e 2 bank: ? word-write (auto erase before program) ? sector-erase (32 words) + word-program (same as flash bank) flash bank: two small erase element sizes ? 1 kwords per sector or 32 kwords per block ? erase either element before word-program cmos i/o compatibility jedec standard command set packages available ? 48-pin tsop (12mm x 20mm) continuous hardware and software data protection (sdp) a one time programmable (otp) e 2 sector product description the sst38vf166 consists of three memory banks, 2 each 512k x16 bits sector mode flash eeprom plus a 4k x16 bits word alterable e 2 prom manufactured with sst ? s pro- prietary, high performance superflash technology. the sst38vf166 erases and programs with a single power supply. the internal erase/program in the e 2 bank is trans- parent to the user. the device conforms to (proposed) jedec standard pinouts for word-wide memories. the sst38vf166 device is divided into three separate memory banks, 2 each 512k x16 flash banks and a 4k x16 e 2 bank. each flash bank is typically used for program code storage and contains 512 sectors, each of 1 kwords or 16 blocks, each of 32 kwords. the flash banks may also be used to store data. the e 2 bank is typically used for data or configuration storage and contains 128 sectors, each of 32 words. any bank may be used for executing code while writing data to a different bank. each memory bank is controlled by separate bank enable (be#) lines. the sst38vf166 inherently uses less energy during erase, program, and write than alternative flash technolo- gies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase, program, or write operation is less than alternative flash technologies. the auto low power mode automatically reduces the active read current to approximately the same as standby; thus, providing an average read current of approximately 1 ma/mhz of read cycle time. the superflash technology provides fixed erase, program, and write times, independent of the number of erase/pro- gram cycles that have occurred. therefore the system soft- ware or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. device operation the sst38vf166 operates as two independent 8-megabit word-program, sector-erase flash eeproms with the additional functionality of a 64 kbit word-alterable e 2 prom. all banks are superimposed in the same mem- ory address space. all three memory banks share com- mon address lines, i/o lines, we#, and oe#. memory bank selection is by bank enable. be#1 selects the first sst38vf16616mb (x16) flashbank + 64kb e 2
2 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 flash bank, be#2 selects the second flash bank, be#3 selects the e 2 bank. we# is used with sdp to control the write or erase and program operation in each memory bank. the sst38vf166 provides the added functionality of being able to simultaneously read from one memory bank while writing, erasing, or programming to one other mem- ory bank. once the internally controlled write, erase, or program cycle in a memory bank has commenced, a differ- ent memory bank can be accessed for read. also, once we# and the applicable be# are high during the sdp load sequence, a different bank may be accessed to read. if multiple bank enables are asserted simultaneously, the out- puts will tri-state and no new memory operations can be initiated. only one bank may be written, erased, or pro- grammed at any given time. the device id and common flash interface (cfi) functions cannot be accessed while any bank is writing, erasing, or programming. the auto low power mode automatically puts the device in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 15ma to typically 3a. the auto low power mode reduces the typical i dd active read current to the range of 1ma/mhz of read cycle time. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. flash bank read the read operation of the sst38vf166 flash bank is controlled by be#1 or be#2 and oe#, a bank enable and output enable both have to be low for the system to obtain data from the outputs. be#1 is used for flash bank 1 selection. when be#1 is high, the flash bank 1 is dese- lected. be#2 is used for flash bank 2 selection. when be#2 is high, the flash bank 2 is deselected. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the timing waveforms for further details (figure 2 or 3). e 2 bank read the read operation of the e 2 bank is controlled by be#3 and oe#, both have to be low for the system to obtain data from the outputs. be#3 is used for e 2 bank selection. when be#3 is high, the e 2 bank is deselected. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when oe# is high. refer to the timing waveforms for further details (figure 4). write modes the sst38vf166 device has separate write modes for the e 2 bank and flash banks. the conventional e 2 prom word-write with internally timed automatic erase before program is the most convenient and easy method for the user to alter data in the e 2 bank with the word-write opera- tion, the word being written is the only word that is altered. bank- or sector-erase plus word-program operations may also be used for the e 2 bank. for both banks of the flash array, the sst38vf166 offers bank-, block-, and sector- erase plus word-program operations. write all write operations are initiated by first issuing the soft- ware data protect (sdp) entry sequence for bank-, block-, or sector-erase then word-program in the selected flash bank; or for word-write or for sector-erase and word-pro- gram in the e 2 bank. word-write, word-program, and all erase commands have a fixed duration, that will not vary over the life of the device, i.e., are independent of the num- ber of erase/program cycles endured. either flash bank may be read during the internally con- trolled e 2 bank write cycle, e.g., the flash bank may be accessed to fetch instructions or data when the e 2 bank is being written, erased, or programmed. additionally, the alternate flash bank may be read while erasing or pro- gramming the other flash or e 2 bank. at any given time, only one bank may be performing a write operation, during that time any other bank is available for read. the write status command may be used to determine if any bank is being written, at any given time. this may be required if the system does not use a timer or does not monitor toggle bit or data# polling when writing a specific bank. in order to implement the write status command, address 5xxxh in the e 2 bank address space is reserved. this address is outside the normal address space of the e 2 bank; therefore, will not interfere with normal reading within the e 2 bank address space. the device is always in the software data protected mode for all write operations in both the flash bank and e 2 bank. write operations are controlled by toggling we# or be#. the falling edge of we# or be#, whichever occurs last, latches the address. the rising edge of we# or be#, whichever occurs last, latches the data and initiates the erase, program, or write cycle. the sdp erase, program, or write commands are all be# specific. whichever be# is used for the first sdp bus cycle (except for read operation with we# high), that be# must be used for all subsequent sdp bus cycles, for the com- mand to be executed. if a different be# is pulsed during a
data sheet 16 megabit flashbank memory sst38vf166 3 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 subsequent bus cycle, when we# is low, in the sdp com- mand sequence, the device will abort the attempted sdp command and revert to the read mode. note, the sdp command sequence may be suspended by taking we# high. a different be# may then be pulsed to read from either of the banks not involved with the sdp command sequence. for the purposes of simplification, the following descrip- tions will assume we# is toggled to initiate an erase, pro- gram, or write. toggling the applicable be# will accomplish the same function. note, there are separate timing dia- grams to illustrate both we# and be# controlled program or write commands. flash bank word-program the flash bank word-program operation consists of issu- ing the sdp word-program command, initiated by forcing be#1 or be#2 and we# low, and oe# high. the words to be programmed must be in the erased state, prior to pro- gramming. the word-program command programs the desired addresses word-by-word. during the word-pro- gram cycle, the addresses are latched by the falling edge of we#. the data is latched by the rising edge of we#. see figure 5 or 7 for we# or 6 and 8 for be# controlled word- program cycle timing waveforms, table 6 for the command sequence, and figure 49 for a flowchart. during the flash bank erase or program operation, the only valid reads from that bank are data# polling and tog- gle bit. the other flash bank or the e 2 bank may be read. the specified bank-, block-, or sector-erase time is the only time required to erase. there are no preprogramming or other commands or cycles required either internally or externally to erase the bank, block, or sector. e 2 bank word-write the e 2 bank word-write operation consists of issuing the sdp command, initiated by forcing be#3 and we# low, and oe# high; followed by the word load cycle to the sst38vf166. the internally controlled write cycle stores the data loaded in the word buffer into the e 2 bank. the address selected is then erased and programmed, by inter- nally controlled signals. during the word load cycle, the address is latched by the falling edge of we#. the data is latched by the rising edge of we#. the internal write cycle is initiated on the rising edge of we#. the write cycle, once initiated, will continue to completion, typically within 7 ms. see figure 9 for we# or 10 for be# controlled write cycle timing waveforms, table 7 for the command sequence, and figure 48 for a flowchart. the write operation has two functional cycles: the word load cycle and the internal write cycle. the word load cycle consists of loading 1 word of data into the word buffer at the completion of the sdp sequence. the internal write cycle consists of the write timer operation, to erase and program the selected address. note, the word does not have to be erased prior to writing. during the write opera- tion, the only valid reads are data# polling and toggle bit from the e 2 bank or normal read from either of the flash banks. e 2 bank word-program the e 2 bank word-program operation consists of issuing the sdp word-program command, initiated by forcing be#3 and we# low and oe# high. the word-program command programs the desired addresses word-by-word. the words to be programmed must be in the erased state, prior to programming, unlike the word-write operation. during the word-program cycle, the addresses are latched by the falling edge of we#. the data is latched by the rising edge of we#. see figure 11 for we# or 12 for be#3 con- trolled program cycle timing waveforms, table 7 for the command sequence and figure 50 for a flowchart. during the e 2 bank erase or program operation, the only valid reads from the bank are data# polling and toggle bit. either flash bank may be read. the specified bank- or sector-erase time is the only time required to erase. there are no preprogramming or other commands or cycles required either internally or externally to erase the bank or sector. erase operations the bank-erase is initiated by a specific six-word load sequence see tables 6 and 7. a bank-erase will typically be less than 70 ms. an alternative to the bank-erase in the flash bank is the block-erase or sector-erase. the block-erase will erase an entire block (32 kwords) in typically 15 ms. the sector- erase will erase an entire sector (1024 words) in typically 15 ms. the sector-erase provides a means to alter a sin- gle sector using the sector-erase and word-program modes. the sector-erase is initiated by a specific six-word load sequence, see table 6. the e 2 bank may also use a sector-erase, instead of bank-erase. an e 2 bank sector consists of 32 words that will typically erase in 7 ms. the sector-erase is initiated by a specific six-word load sequence, see table 7. sector- or bank-erase and word-program is an alternative to word- write as a means to alter the e 2 bank.
4 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 during any sector-, block-, or bank-erase within a bank, any other bank may be read. during the word-write of the e 2 bank, either flash bank may be read. flash bank bank-erase the sst38vf166 provides a flash bank-erase mode, which allows the user to clear the flash bank to the ? 1 ? state. this is useful when the entire flash must be quickly erased. the software flash bank-erase mode is initiated by issuing the specific six-word loading sequence, as in the software data protection operation. after the loading cycle, the device enters into an internally timed cycle. see table 6 for specific codes, figure 13 or 16 for the timing waveform, and figure 44 for a flowchart. flash bank block-erase the sst38vf166 provides a block-erase mode, which allows the user to clear any block in the flash bank to the ? 1 ? state. the software block-erase mode is initiated by issuing the specific six-word loading sequence, as in the software data protect operation. after the loading cycle, the device enters into an internally timed erase cycle. see table 6 for specific codes, figure 14 or 17 for the timing waveform, and figure 45 for a flowchart. during the erase operation, the only valid reads are data# polling and toggle bit from the selected bank, other banks may perform normal read. flash bank sector-erase the sst38vf166 provides a sector-erase mode, which allows the user to clear any sector in the flash bank to the ? 1 ? state. the software sector-erase mode is initiated by issuing the specific six-word loading sequence, as in the software data protect operation. after the loading cycle, the device enters into an internally timed erase cycle. see table 6 for specific codes, figure 15 or 18 for the timing waveform, and figure 47 for a flowchart. during the erase operation, the only valid reads are data# polling and toggle bit from the selected bank, other banks may perform normal read. e 2 bank bank-erase the sst38vf166 provides a e 2 bank-erase mode, which allows the user to clear the e 2 bank to the ? 1 ? state. this is useful when the entire e 2 bank must be quickly erased. the e 2 bank bank-erase command is disabled if the e 2 bank otp option is enabled. the e 2 bank-erase mode is initiated by issuing the specific six-word loading sequence, as in the software data pro- tection operation. after the loading cycle, the device enters into an internally timed cycle. see table 7 for specific codes, figure 19 for the timing waveform, and figure 44 for a flowchart. e 2 bank sector-erase the sst38vf166 provides a sector-erase mode, which allows the user to clear any sector in the e 2 bank to the ? 1 ? state. the software sector-erase mode is initiated by issu- ing the specific six-word loading sequence, as in the soft- ware data protect operation. after the loading cycle, the device enters into an internally timed. see tables 6 and 7 for specific codes, figure 20 for the timing waveform, and figure 46 for a flowchart. during the erase operation, the only valid reads are data# polling and toggle bit in the e 2 bank or normal read from either of the flash banks. write operation status detection the sst38vf166 provides two software means to detect the completion of a e 2 bank or a flash bank program cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which ini- tiates the internal write, erase, or program cycle. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system will possibly get an erroneous result, i.e. valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious device rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. additionally, a write status read may be executed to deter- mine if any bank has an erase, program, or write opera- tion in progress. a write status read may be used when, for any reason, the system may have lost track of the status of a write, erase, or program operation in any bank. although normally, a word-write, word-program, sector- erase, or block-erase will be completed prior to recovery from a system reset, if a bank-erase was initiated prior to the reset, the system may need to verify the bank-erase is no longer in progress. note, a bank-erase will not be per- formed on the bank containing the boot code, so there will
data sheet 16 megabit flashbank memory sst38vf166 5 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 be no issue when recovering from the system reset. see table 6 or 7 for the specific codes and figure 40 for a timing waveform. there is no provision to abort an erase, program, or write operation, once initiated. for the sst superflash technol- ogy, the associated erase, program, and write times are so fast, relative to system reset times, there is no value in aborting the operation. note, reads can always occur from any bank not performing an erase, program, or write oper- ation. should the system reset, while a block- or sector-erase or word-program is in progress in the bank where the boot code is stored, the system must wait for the completion of the operation before reading that bank. since the maxi- mum time the system would have to wait is 25 ms (for a block-erase), the system ability to read the boot code would not be affected. data# polling (dq 7 ) - flash bank when the sst38vf166 is in the internal flash bank pro- gram cycle, any attempt to read dq 7 of the last word loaded during the flash bank word load cycle will receive the complement of the true data. once the write cycle is completed, dq 7 will show true data. the device is then ready for the next operation. see figure 21 or 22 for the flash bank data polling timing waveforms and figure 51 for a flowchart. data# polling (dq 7 ) - e 2 bank when the sst38vf166 is in the internal e 2 bank write cycle, any attempt to read dq 7 of the last word loaded dur- ing the e 2 bank word load cycle will receive the comple- ment of the true data. once the write cycle is completed, dq 7 will show true data. the device is then ready for the next operation. see figure 23 for e 2 bank data polling tim- ing waveforms and figure 51 for a flowchart. toggle bit (dq 6 ) - flash bank during the flash bank internal write cycle, any consecutive attempts to read dq 6 will produce alternating 0s and 1s, i.e. toggling between 0 and 1. when the write cycle is com- pleted, the toggling will stop. the device is then ready for the next operation. see figure 24 or 25 for flash bank tog- gle bit timing waveforms and figure 51 for a flowchart. toggle bit (dq 6 ) - e 2 bank during the e 2 bank internal write cycle, any consecutive attempts to read dq 6 will produce alternating 0s and 1s, i.e. toggling between 0 and 1. when the write cycle is com- pleted, the toggling will stop. the device is then ready for the next operation. see figure 26 for e 2 bank toggle bit timing waveforms and figure 51 for a flowchart. data protection the sst38vf166 provides both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5 volts. write inhibit mode: forcing oe# low, be#1 and be#2 high, or we# high will inhibit the write operation to the flash bank. forcing oe# low, be#3 high, or we# high will inhibit the write operation to the e 2 bank. this prevents inadvert- ent writes during power-up or power-down. a one time programmable e 2 sector the first sector of the e 2 bank offers the option of otp (one time programmable) prevention of write for the first sector, i.e., addresses a 5 to a 13 are ? 0 ? (0000h to 001fh). once the otp software instruction is executed, no write, erase, or program operation can be performed on these 32 words. this is permanent and non-reversible. additionally, if the otp prevention is enabled, the bank-erase for the e 2 bank will not function. see table 7 for specific codes and figure 39 for a timing waveform. software data protection (sdp) the sst38vf166 provides the jedec approved software data protection scheme as a requirement for initiating a write, erase, or program operation. with this scheme, any write operation requires the inclusion of a series of three word-load operations to precede the word-write or word- program operation. the three-word load sequence is used to initiate the write or program cycle, providing optimal pro- tection from inadvertent write operations, e.g., during the system power-up or power-down. the six-word sequence is required to initiate any bank-, block-, or sector-erase operation.
6 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 the requirements for jedec compliant sdp are in byte format. the sst38vf166 is organized by word; therefore, the contents of dq 8 to dq 15 are ? don ? t care ? during any sdp (3-word or 6-word) command sequence. during the sdp load command sequence, the sdp load cycle is suspended when we# is high. this means a read may occur to any other bank during the sdp load sequence. the sdp load sequence is bank specific, i.e., the same be# must be low for each bus cycle. if the command sequence is aborted, e.g., a different be# is brought low (except for read operation with we# high), an incorrect address is loaded, or incorrect data is loaded, the device will return to the read mode within t rc of execution of the load error. concurrent read and write operations the sst38vf166 provides the unique benefit of being able to read any bank, while simultaneously writing, eras- ing, or programming one other bank. this allows data alter- ation code to be executed from one bank, while altering the data in another bank. the following table lists all valid states. note: for the purposes of this table, write means to word-write; block-, sector-, or chip-erase; or word-program as applica- ble to the appropriate bank. sst does not recommend that any two of the bank enable signals be#1, be#2 or be#3 be simultaneously asserted. the device will ignore all sdp commands and toggling of we# when an erase, program, or write operation is in progress. note, both product identification and the com- mon flash interface entry commands use sdp; therefore, these commands will also be ignored while an erase, pro- gram, or write operation is in progress. product identification the product identification mode identifies the device manu- facturer as sst and provides a code to identify each bank. the manufacturer id is the same for each bank; however, each bank has a separate device id. each bank is individu- ally accessed using the applicable be# and a software command. users may wish to use the device id operation to identify the write algorithm requirements for each bank. for details, see table 6 or 7 for software operation and fig- ures 27, 28, or 29 for timing waveforms. device ids are unique to each bank. should a chip id be required, any of the bank ids may be used as the chip id. while in the read software id mode or cfi mode, no other operation is allowed until after exiting these modes. product identification mode exit in order to return to the standard read mode, the product identification mode must be exited. exit is accomplished by issuing the software id exit command, which returns the device to normal operation. this command may also be used to reset the device to the read mode after any inad- vertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. for details, see table 6 or 7 for software operation and figures 30, 31, or 32 for timing waveforms. tab le 1: c oncurrent r ead /w rite s tate flash bank 1 flash bank 2 e 2 bank read no operation write read write no operation write read no operation no operation read write write no operation read no operation write read t1.0 327 tab le 2: p roduct i dentification address data manufacturer ? s id 0000h 00bfh device id flash bank 1 0001h 2791h flash bank 2 0001h 2792h e 2 bank 0001h 2793h t2.1 327
data sheet 16 megabit flashbank memory sst38vf166 7 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 common flash interface (cfi) the sst38vf166 also contains the cfi information in each bank, to describe the characteristics of that bank. see tables 8 through 16 for the cfi contents for each bank. both flash banks use the same information, as each bank operates the same. the e 2 bank contains the applicable information for that bank. in order to obtain the cfi information, the cfi memory space is accessed by using the cfi entry command. for details, see table 6 or 7 for software operation and figures 33, 34, or 35 for timing waveforms. cfi mode exit in order to return to the standard read mode, the cfi mode must be exited. exit is accomplished by issuing the cfi exit command, which returns the device to normal operation. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. for details, see table 6 or 7 for software operation and figures 36, 37, or 38 for tim- ing waveforms. cfi is specified for byte wide information. since the sst38vf166 is organized word wide, the first byte (2 nib- bles) of each cfi word is always 00h. 327 ill f02.1 i/o buffers and data latches 512k x 16 flash bank 2 4k x 16 e 2 bank 512k x 16 flash bank 1 x - decoder control logic address buffer and latches oe# be#1 be#2 be#3 we# a 18 - a 0 dq 15 - dq 0 charge pump & vref. y - decoder f unctional b lock d iagram
8 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 1: p in a ssignments for 48-p in tsop (12 mm x 20 mm ) tab le 3: p in d escription symbol name functions a 18 -a 0 flash bank addresses to provide flash bank addresses a 11 -a 0 e 2 bank addresses to provide e 2 bank addresses a 18 -a 15 flash bank block addresses to select a flash bank block for erase a 18 -a 10 flash bank sector addresses to select a flash bank sector for erase a 11 -a 5 e 2 bank sector addresses to select an e 2 bank sector for erase dq 15 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# is high or be#1, be#2, and be#3 are high. oe# output enable to gate the data output buffers we# write enable 1 to control the write, erase, or program operations v dd power supply to provide 2.7-3.6v power supply v ss ground nc no connect unconnected pins t3.4 327 a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# nc be#2 nc be#3 a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss be#1 a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 327 ill f01b.5 standard pinout top view die up
data sheet 16 megabit flashbank memory sst38vf166 9 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 tab le 4: o peration m odes s election for f lash b ank array operation mode be#1 be#2 be#3 oe# we# dq address read flash bank 1 v il v ih v ih v il v ih d out a in flash bank 2 v ih v il v ih v il v ih d out a in block-erase flash bank 1 v il v ih v ih v ih v il d in see tables 6 and 7 flash bank 2 v ih v il v ih v ih v il d in see tables 6 and 7 sector-erase flash bank 1 v il v ih v ih v ih v il d in see tables 6 and 7 flash bank 2 v ih v il v ih v ih v il d in see tables 6 and 7 program flash bank 1 v il v ih v ih v ih v il d in see tables 6 and 7 flash bank 2 v ih v il v ih v ih v il d in see tables 6 and 7 standby v ih v ih v ih x x high z x write inhibit flash bank 1 v ih xxv il v ih xx flash bank 2 x v ih xv il v ih xx flash bank-erase flash bank 1 v il v ih v ih v ih v il d in see tables 6 and 7 flash bank 2 v ih v il v ih v ih v il d in see tables 6 and 7 status operation mode be#1 be#2 be#3 oe# we# dq address write status read v ih v ih v il v il v ih d out 1 5xxxxh illegal state v il v il v il x x high z x 2 illegal state v il v il x x x high z x 2 illegal state v il xv il x x high z x 2 illegal state x v il v il x x high z x 2 product identification flash bank 1 v il v ih v ih v il v ih d out see tables 6 and 7 flash bank 2 v ih v il v ih v il v ih d out see tables 6 and 7 common flash interface flash bank 1 v il v ih v ih v il v ih d out see tables 6 and 7 flash bank 2 v ih v il v ih v il v ih d out see tables 6 and 7 t4.5 327 1. if flash bank 1 is writing, dq 1 is low. if flash bank 2 is writing, dq 2 is low. if e 2 bank is writing, dq 3 is low. 2. entering an illegal state during an erase, program, or write operation will not affect the operation, i.e., the erase, progra m, or write will continue to normal completion.
10 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 tab le 5: o peration m odes s election for e 2 b ank read operation mode be#1 be#2 be#3 oe# we# dq address read e 2 bank v ih v ih v il v il v ih d out 1 write e 2 bank v ih v ih v il v ih v il d in see tables 6 and 7 sector-erase e 2 bank v ih v ih v il v ih v il d in see tables 6 and 7 program e 2 bank v ih v ih v il v ih v il d in see tables 6 and 7 standby v ih v ih v ih xxd in see tables 6 and 7 write inhibit e 2 bank x x v ih v il v ih high z x erase e 2 bank v ih v ih v il v ih v il d in see tables 6 and 7 otp enable e 2 bank v ih v ih v il v ih v il d in see tables 6 and 7 status operation mode be#1 be#2 be#3 oe# we# dq address write status read v ih v ih v il v il v ih d out 2 5xxxxh illegal state v il v il v il x x high z x 3 illegal state v il v il x x x high z x 3 illegal state v il xv il x x high z x 3 illegal state x v il v il x x high z x 3 product identification e 2 bank v ih v ih v il v il v ih d out see tables 6 and 7 common flash interface e 2 bank v ih v ih v il v il v ih d out see tables 6 and 7 t5.6 327 1. a 11 -a 0 are valid addresses; a 15 -a 12 are ? don ? t care ? ; a 18 -a 16 cannot be 5h 2. if flash bank 1 is writing, dq 1 is low. if flash bank 2 is writing, dq 2 is low. if e 2 bank is writing, dq 3 is low. 3. entering an illegal state during an erase, program, or write operation will not affect the operation, i.e., the erase, progra m, or write will continue to normal completion.
data sheet 16 megabit flashbank memory sst38vf166 11 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 tab le 6: s oftware c ommand s equence for f lash b anks command code 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 software id entry 5555h aah 2aaah 55h 5555h 90h 3 software id exit 5555h aah 2aaah 55h 5555h f0h 4 flash bank word-program 5555h aah 2aaah 55h 5555h a0h wa 5 data in flash bank sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 6 30h flash bank block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba 6 50h flash bank bank-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h cfi entry 5555h aah 2aaah 55h 5555h 98h 7 cfi exit 5555h aah 2aaah 55h 5555h f0h 4 t6.4 327 1. command code address format a 14 -a 0 (hex), addresses > a 14 are ? don ? t care ? for command sequences 2. data format dq 7 -dq 0 (hex), dq 15 - dq 8 are ? don ? t care ? 3. with a 14 -a 1 = 0; sst manufacturer ? s id = 00bfh, is read with a 0 = 0 sst38vf166 device id = 2791h, 2792h, and 2793h is read with a 0 = 1 for the applicable be# active 4. the device does not remain in software product id mode or cfi mode if powered down. 5. wa = word address 6. sa = sector address ba = block address 7. there is a separate cfi for each bank. see tables 8 through 16 tab le 7: s oftware c ommand s equence for e 2 b anks command code 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr 1 1. command code address format a 14 -a 0 (hex), addresses > a 14 are ? don ? t care ? for command sequences data 2 2. data format dq 7 -dq 0 (hex), dq 15 - dq 8 are ? don ? t care ? addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 software id entry 5555h aah 2aaah 55h 5555h 90h 3 3. with a 14 -a 1 = 0; sst manufacturer ? s id = 00bfh, is read with a 0 = 0 sst38vf166 device id = 2791h, 2792h, and 2793h is read with a 0 = 1 for the applicable be# active software id exit 5555h aah 2aaah 55h 5555h f0h 4 4. the device does not remain in software product id mode or cfi mode if powered down. e 2 bank word-write 5555h aah 2aaah 55h 5555h a0h wa 5 5. wa = word address data in e 2 bank word-program 5555h aah 2aaah 55h 5555h a5h wa 5 data in e 2 bank sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 6 6. sa = sector address 30h e 2 bank bank-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h e 2 bank otp enable 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 70h cfi entry 5555h aah 2aaah 55h 5555h 98h 7 7. there is a separate cfi for each bank. see tables 8 through 16 cfi exit 5555h aah 2aaah 55h 5555h f0h 4 t7.4 327
12 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 tab le 8: cfi q uery i dentification s tring for f lash b ank 1 address data data 10h 0051h query unique ascii string ? qry ? 11h 0052h 12h 0059h 13h 0001h primary oem command set (jep-137) 14h 0008h 15h 0000h address for primary extended table (00h = none exists) 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t8.2 327 tab le 9: s ystem i nterface i nformation for f lash b ank 1 address data data 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0004h typical time out for word-program 2 n s 20h 0000h typical time out for min. size page-write 2 n s (00h = not supported) 21h 0004h typical time out for individual sector-erase 2 n ms 22h 0006h typical time out for bank-erase 2 n ms 23h 0001h maximum time out for word-program 2 n times typical 24h 0000h maximum time out for page-write 2 n times typical (00h = not supported) 25h 0001h maximum time out for individual sector-erase 2 n times typical 26h 0001h maximum time out for chip-erase 2 n times typical t9.7 327 tab le 1 0: d evice g eometry i nformation for f lash b ank 1 address data data 27h 0014h bank size = 2 n byte (14h > 2 20 = 1 mbyte = 8 mbits) 28h 0001h flash bank device interface description (refer to cfi jesd-68) (x16 asynchronous) 29h 0000h 2ah 0000h maximum number of bytes in page-write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase block regions within device 2dh 00ffh erase block region 1 information (sector) 2eh 0001h (refer to the cfi specification or jesd-68) 2fh 0008h y = 511 + 1 = 512 sectors (01ffh = 511) 30h 0000h z = 2 kbytes/sector = 8 x 256 bytes 31h 000fh erase block region 2 information (block) 32h 0000h (refer to the cfi specification or jesd-68) 33h 0000h y = 15 + 1 = 16 blocks 34h 0001h z = 64 kbytes/block = 256 x 256 bytes (0100h = 64k) t10.5 327
data sheet 16 megabit flashbank memory sst38vf166 13 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 tab le 1 1: cfi q uery i dentification s tring for f lash b ank 2 address data data 10h 0051h query unique ascii string ? qry ? 11h 0052h 12h 0059h 13h 0001h primary oem command set (jep-137) 14h 0008h 15h 0000h address for primary extended table (00h = none exists) 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t11.2 327 tab le 1 2: s ystem i nterface i nformation for f lash b ank 2 address data data 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0004h typical time out for word-program 2 n s 20h 0000h typical time out for min. size page-write 2 n s (00h = not supported) 21h 0004h typical time out for individual sector-erase 2 n ms 22h 0006h typical time out for bank-erase 2 n ms 23h 0001h maximum time out for word-program 2 n times typical 24h 0000h maximum time out for page-write 2 n times typical (00h = not supported) 25h 0001h maximum time out for individual sector-erase 2 n times typical 26h 0001h maximum time out for chip-erase 2 n times typical t12.8 327 tab le 1 3: d evice g eometry i nformation for f lash b ank 2 address data data 27h 0014h bank size = 2 n byte (14h > 2 20 = 1 mbyte = 8 mbits) 28h 0001h flash bank device interface description (refer to cfi jesd-68) (x16 asynchronous) 29h 0000h 2ah 0000h maximum number of bytes in page-write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase block regions within device 2dh 00ffh erase block region 1 information (sector) 2eh 0001h (refer to the cfi specification or jesd-68) 2fh 0008h y = 511 + 1 = 512 sectors (01ffh = 511) 30h 0000h z = 2 kbytes/sector = 8 x 256 bytes 31h 000fh erase block region 2 information (block) 32h 0000h (refer to the cfi specification or jesd-68) 33h 0000h y = 15 + 1 = 16 blocks 34h 0001h z = 64 kbytes/block = 256 x 256 bytes (0100h = 64k) t13.5 327
14 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 tab le 1 4: cfi q uery i dentification s tring for e 2 b ank address data data 10h 0051h query unique ascii string ? qry ? 11h 0052h 12h 0059h 13h 0001h primary oem command set (jep-137) 14h 0009h 15h 0000h address for primary extended table (00h = none exists) 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t14.1 327 tab le 1 5: s ystem i nterface i nformation for e 2 b ank address data data 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min. (00h = no v pp pin) 1eh 0000h v pp max. (00h = no v pp pin) 1fh 0005h typical time out for word-program 2 n s 20h 0000h typical time out for min. size page-write 2 n s (00h = not supported) 21h 0003h typical time out for individual sector-erase 2 n ms 22h 0006h typical time out for bank-erase 2 n ms 23h 0001h maximum time out for word-program 2 n times typical 24h 0000h maximum time out for page-write 2 n times typical (00h = not supported) 25h 0001h maximum time out for individual sector-erase 2 n times typical 26h 0001h maximum time out for chip-erase 2 n times typical t15.7 327 tab le 1 6: d evice g eometry i nformation for e 2 b ank address data data 27h 000dh device size = 2 n byte (dh > 2 13 = 8 kbytes = 64 kbits) 28h 0001h flash bank device interface description (refer to cfi jesd-68) (x16 asynchronous) 29h 0000h 2ah 0001h maximum number of bytes in page-write = 2 n (00h = not supported) 2bh 0000h 2ch 0001h number of erase block regions within device 2dh 007fh erase block region 1 information (sector) 2eh 0000h (refer to the cfi specification or jesd-68) 2fh 0001h y = 127 + 1 = 128 sectors (007fh = 127) 30h 0000h z = 32 bytes/sector = 1 x 256 bytes t16.4 327
data sheet 16 megabit flashbank memory sst38vf166 15 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 absolute maximum stress ratings (applied conditions greater than those listed under ? absolute maximum stress ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to +150 c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd + 0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd + 1.0v package power dissipation capability (ta = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange : range ambient temp v dd commercial 0 c to +70 c2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 10 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 42 and 43 tab le 1 7: dc o perating c haracteristics v dd = 2.7-3.6v symbol parameter limits test conditions min max units i dd power supply current address input = v il /v ih , at f=1/t rc min v dd =v dd max read 35 ma be#1,be#2, or be#3=v il , we#=v ih , all i/os open write: flash bank 40 ma be#1/2=we#=v il , oe#=v ih v dd =v dd max or e 2 bank be#3=we#=v il , oe#=v ih v dd =v dd max read: flash bank plus write/program/erase: e2 bank or flash bank 75 ma address input = v il /v ih , at f=1/t rc min we#=v ih , v dd =v dd max be#1,be#2, or be#3=v il , oe#=we#=v ih , i sb standby v dd current (cmos inputs) 50 a be#1,be#2, or be#3=v ihc , v dd = v dd max i alp auto low power mode (cmos inputs) 50 a be#1,be#2, or be#3=v ilc , we#= v ihc , all i/os open, address input = v ihc /v ihc and static v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd = v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd = v dd max v il input low voltage 0.3v dd vv dd = v dd min v ilc input low voltage (cmos) 0.2 v v ih input high voltage 0.7v dd vv dd = v dd max v ihc input high voltage (cmos) v dd -0.2 v v dd = v dd max v ol output low voltage 0.2 v i ol = 100 a, v dd = v dd min v oh output high voltage v dd -0.2 v i oh = -100 a, v dd = v dd min t17.1 327
16 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 tab le 1 8: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t18.1 327 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. tab le 1 9: c apacitance (ta = 25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t19.1 327 tab le 2 0: r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. endurance - flash bank endurance - e2 bank 10,000 100,000 cycles/sector cycles/word jedec standard a117 t dr 1 data retention 100 years jedec standard a103 v zap_hbm 1 esd susceptibility human body model 2000 volts jedec standard a114 v zap_mm 1 esd susceptibility machine model 200 volts jedec standard a115 i lt h 1 latch up 100 + i dd ma jedec standard 78 t20.0 327
data sheet 16 megabit flashbank memory sst38vf166 17 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 ac characteristics tab le 2 1: r ead c ycle t iming p arameters symbol parameter sst38vf166-70 units min max t rc read cycle time 70 ns t be bank enable access time 70 ns t aa address access time 70 ns t oe output enable access time 30 ns t clz 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t21.1 327 tab le 2 2: w rite , e rase , p rogram c ycle t iming p arameters symbol parameter min max units t wc word-write cycle (erase and program) 12.5 ms t bpe word-program time - e 2 bank 40 s t bpf word-program time - flash bank 20 s t sef sector-erase time - flash bank 25 ms t lef block-erase time - flash bank 25 ms t bef bank-erase time - flash bank 100 ms t see sector-erase time - e 2 bank 12.5 ms t bee bank-erase time - e 2 bank 100 ms t as address setup time 0 ns t ah address hold time 40 ns t bes be# setup time 0 ns t beh be# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 0 ns t wp write pulse low width 40 ns t wph write pulse high time 30 ns t ds data setup time 40 ns t dh data hold time 0 ns t vddr 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. v dd rise time 0.1 50 ms t dbr time to data# polling read 35 ns t tbr time to toggle bit read 35 ns t ida time to id or cfi read/exit cycle 150 ns t bs bank enable setup time for concurrent operation 0 ns t22.0 327
18 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 timing diagrams address and data format are in hexadecimal figure 2: f lash b ank 1, r ead c ycle t iming d iagram figure 3: f lash b ank 2, r ead c ycle t iming d iagram 327 ill f03a.2 address a 18-0 dq 15-0 be#2, be#3, we# oe# be#1 t be t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 327 ill f03b.2 address a 18-0 dq 15-0 be#1 , be#3, we# oe# be#2 t be t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz
data sheet 16 megabit flashbank memory sst38vf166 19 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 4: e 2 b ank , r ead c ycle t iming d iagram figure 5: f lash b ank 1, we# c ontrolled w ord -p rogram c ycle t iming d iagram 327 ill f03c.2 address a 11-0 dq 15-0 be#1 , be#2, we# oe# be#3 t be t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 327 ill f04a1.3 address a 18-0 dq 150 t dh t wph t ds t wp t ah t as t beh t bes be#1 sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts word (addr/data) be#2, be#3, oe# we# t bpf
20 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 6: f lash b ank 1, be# c ontrolled w ord -p rogram c ycle t iming d iagram figure 7: f lash b ank 2, we# c ontrolled w ord -p rogram c ycle t iming d iagram 327 ill f04a2.3 address a 18-0 dq 150 t dh t wph t ds t wp t ah t as t weh t wes we#1 sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts word (addr/data) be#2, be#3, oe# be#1 t bpf 327 ill f04b1.3 address a 18-0 dq 15-0 t dh t wph t ds t wp t ah t as t beh t bes be#2 sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts word (addr/data) be#1, be#3, oe# we# t bpf
data sheet 16 megabit flashbank memory sst38vf166 21 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 8: f lash b ank 2, be# c ontrolled w ord -p rogram c ycle t iming d iagram figure 9: e 2 b ank , we# c ontrolled w ord -w rite c ycle t iming d iagram 327 ill f04b2.3 address a 18-0 dq 15-0 t dh t wph t ds t wp t ah t as t weh t wes we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts word (addr/data) be#1, be#3, oe# be#2 t bpf 327 ill f04c1.3 address a 14-0 dq 15-0 t dh t wph t ds t wp t ah t as t beh t bes be#3 sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts word (addr/data) be#1, be#2, oe# we# t wc
22 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 10: e 2 b ank , be# c ontrolled w ord -w rite c ycle t iming d iagram figure 11: e 2 b ank , we# c ontrolled w ord -p rogram c ycle t iming d iagram 327 ill f04c2.3 address a 14-0 dq 15-0 t dh t wph t ds t wp t ah t as t weh t wes we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts word (addr/data) be#1, be#2, oe# be#3 t wc 327 ill f04d1.3 address a 14-0 dq 15-0 t dh t wph t ds t wp t ah t as t beh t bes be#3 sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a5 data internal program operation starts word (addr/data) be#1, be#2, oe# we# t bpe
data sheet 16 megabit flashbank memory sst38vf166 23 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 12: e 2 b ank , be# c ontrolled w ord -p rogram c ycle t iming d iagram figure 13: f lash b ank 1, b ank -e rase t iming d iagram 326 ill f04d 2.3 address a 14-0 dq 15-0 t dh t wph t ds t wp t ah t as t weh t wes we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a5 data internal program operation starts word (addr/data) be#1, be#2, oe# be#3 t bpe 327 ill f05a1.2 address a 18-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 be#2, be#3, oe# be#1 six-byte code for bank-erase t bef t wp t ah t as t wph t dh t ds
24 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 14: f lash b ank 1, b lock -e rase t iming d iagram figure 15: f lash b ank 1, s ector -e rase t iming d iagram 327 ill f05a2.3 address a 18-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 50 55 aa 80 aa b ax be#2, be#3, oe# be#1 six-byte code for block-erase t lef t wp t ah t as t wph t dh t ds 327 ill f05a3.3 address a 18-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa s ax be#2, be#3, oe# be#1 six-byte code for sector-erase t sef t wp t ah t as t wph t dh t ds
data sheet 16 megabit flashbank memory sst38vf166 25 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 16: f lash b ank 2, b ank -e rase t iming d iagram figure 17: f lash b ank 2, b lock -e rase t iming d iagram 327 ill f05b1.2 address a 18-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 be#1, be#3, oe# be#2 six-byte code for bank-erase t bef t wp t ah t as t wph t dh t ds 327 ill f05b2.4 address a 18-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 50 55 aa 80 aa b ax be#1, be#3, oe# be#2 six-byte code for block-erase t lef t wp t ah t as t wph t dh t ds
26 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 18: f lash b ank 2, s ector -e rase t iming d iagram figure 19: e 2 b ank , b ank -e rase t iming d iagram 327 ill f05b3.3 address a 18-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa s ax be#1, be#3, oe# be#2 six-byte code for sector-erase t sef t wp t ah t as t wph t dh t ds 327 ill f05c1.2 address a 14-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 be#1, be#2, oe# be#3 six-byte code for bank-erase t bee t wp t ah t as t wph t dh t ds
data sheet 16 megabit flashbank memory sst38vf166 27 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 20: e 2 b ank , s ector -e rase t iming d iagram figure 21: f lash b ank 1, d ata # p olling t iming d iagram 327 ill f05c2.3 address a 14-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa s ax be#1, be#2, oe# be#3 six-byte code for sector-erase t see t wp t ah t as t wph t dh t ds 326 ill f06a.3 dq 7 data data# data# data t oeh t oe t be t oes address a 18-0 we# be#2, be#3 oe# be#1
28 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 22: f lash b ank 2, d ata # p olling t iming d iagram figure 23: e 2 b ank , d ata # p olling t iming d iagram 327 ill f06b.3 dq 7 data data# data# data t oeh t oe t be t oes address a 18-0 we# oe# be#2 be#1, be#3 327 ill f06c.3 dq 7 data data# data# data t oeh t oe t be t oes address a 14-0 we# oe# be#3 be#1, be#2
data sheet 16 megabit flashbank memory sst38vf166 29 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 24: f lash b ank 1, t oggle b it t iming d iagram figure 25: f lash b ank 2, t oggle b it t iming d iagram 327 ill f07a.3 address a 18-0 dq 6 we# oe# be#1 t oe t oeh t be t oes two read cycles with same outputs be#2, be#3 327 ill f07b.3 address a 18-0 dq 6 we# oe# be#2 t oe t oeh t be t oes two read cycles with same outputs be#1, be#3
30 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 26: e 2 b ank , t oggle b it t iming d iagram figure 27: f lash b ank 1, s oftware id e ntry and r ead 326 ill f07c.3 address a 14 -0 dq 6 we# oe# be#3 t oe t oeh t be t oes two read cycles with same outputs be#1, be#2 327 ill f08a.5 address a 14-0 t ida dq 15-0 we# oe# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 be#1 three-byte sequence for software id entry t wp t wph t aa 00bf 55 aa 90 be#2, be#3 2791
data sheet 16 megabit flashbank memory sst38vf166 31 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 28: f lash b ank 2, s oftware id e ntry and r ead figure 29: e 2 b ank , s oftware id e ntry and r ead 327 ill f08b.5 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 be#2 three-byte sequence for software id entry t wp t wph t aa 00bf 55 aa 90 oe# be#1, be#3 2792 327 ill f08c.5 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 be#3 three-byte sequence for software id entry t wp t wph t aa 00bf 2793 55 aa 90 be#2, be#3 oe#
32 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 30: f lash b ank 1, s oftware id e xit figure 31: f lash b ank 2, s oftware id e xit 327 ill f09a.3 address a 14-0 dq 15-0 t ida t wp t wph we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit be#2, be#3, oe# be#1 aa 55 f0 327 ill f09b.4 address a 14-0 dq 15-0 t ida t wp t wph we# sw0 sw1 sw2 5555 2aaa 5555 be#1 , be#3, oe# be#1 aa 55 f0 three-byte sequence for software id exit
data sheet 16 megabit flashbank memory sst38vf166 33 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 32: e 2 b ank , s oftware id e xit figure 33: f lash b ank 1, cfi e ntry and r ead 327 ill f09c.4 address a 14 -0 dq 15-0 t ida t wp t wph we# sw0 sw1 sw2 5555 2aaa 5555 be#1 , be#3, oe# be#1 aa 55 f0 three-byte sequence for software id exit 327 ill f10a.2 address a 14-0 t ida dq 15-0 we# oe# sw0 sw1 sw2 5555 2aaa 5555 0010 0011 be#1 three-byte sequence for cfi entry t wp t wph t aa 0051 0052 55 aa 98 be#2, be#3
34 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 34: f lash b ank 2, cfi e ntry and r ead figure 35: e 2 b ank , cfi e ntry and r ead 327 ill f10b.3 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0010 0011 be#2 three-byte sequence for cfi entry t wp t wph t aa 0051 0052 55 aa 98 oe# be#1, be#3 327 ill f10c.3 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0010 0011 be#3 three-byte sequence for cfi entry t wp t wph t aa 0051 0052 55 aa 98 be#2, be#3 oe#
data sheet 16 megabit flashbank memory sst38vf166 35 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 36: f lash b ank 1, cfi e xit figure 37: f lash b ank 2, cfi e xit 327 ill f11a.2 address a 14-0 dq 15-0 t ida t wp t wph we# sw0 sw1 sw2 5555 2aaa 5555 be#2, be#3, oe# be#1 aa 55 f0 three-byte sequence for cfi exit 327 ill f11b.3 address a 14-0 dq 15-0 t ida t wp t wph we# sw0 sw1 sw2 5555 2aaa 5555 be#1 , be#3, oe# be#1 aa 55 f0 three-byte sequence for cfi exit
36 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 38: e 2 b ank , cfi e xit figure 39: e 2 b ank , otp e nable 327 ill f11c.3 address a 14 -0 dq 15-0 t ida t wp t wph we# sw0 sw1 sw2 5555 2aaa 5555 be#1 , be#3, oe# be#1 aa 55 f0 three-byte sequence for cfi exit 327 ill f12.2 address a 14 -0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 70 55 aa 80 aa 5555 be#1, be#2, oe# be#3 six-byte code for otp enable t bpe t wp t ah t as t wph t dh t ds
data sheet 16 megabit flashbank memory sst38vf166 37 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 40: w rite o peration s tatus r ead figure 41: t iming d iagram to a lternate b etween e ach m emory b ank 327 ill f13.3 address a 18-0 dq 15-0 be#1, be#2, we# oe# be#3 t be t rc t aa t oe t olz v ih high-z t clz t oh data valid 5xxxx 327 ill f25.1 address a 18-0 t bs dq 15-0 be#i be#i we# oe# note: i = 1, 2, 3
38 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 42: ac i nput /o utput r eference w aveforms figure 43: a t est l oad e xample 327 ill f14.3 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ? 1 ? and v ilt (0.1 v dd ) for a logic ? 0 ? . measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <10 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 327 ill f15.3 to tester to dut c l
data sheet 16 megabit flashbank memory sst38vf166 39 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 44: b ank -e rase f lowchart memory bank bank-erase start software data protect bank-erase command wait for end-of-erase (t bee , t bef , data # polling, or toggle bit) bank-erase complete 327 ill f16.3
40 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 45: f lash b ank b lock -e rase f lowchart flash bank block-erase start software data protect block-erase flash bank command set block address wait for end-of-erase (t lef , data # polling, or toggle bit) 327 ill f17.5 flash bank block-erase complete
data sheet 16 megabit flashbank memory sst38vf166 41 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 46: e 2 b ank s ector -e rase f lowchart e 2 bank sector-erase start software data protect sector-erase flash bank command set sector address wait for end-of-erase (t see , data # polling, or toggle bit) 327 ill f18.5 e 2 bank sector-erase complete
42 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 47: f lash b ank s ector -e rase f lowchart flash bank sector-erase start software data protect sector-erase flash bank command set sector address wait for end-of-erase (t sef , data # polling, or toggle bit) 327 ill f19.5 flash bank sector-erase complete
data sheet 16 megabit flashbank memory sst38vf166 43 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 48: e 2 b ank w ord -w rite f lowchart e 2 bank word-write start software data protect write e 2 bank command set word address load word data e 2 bank word-write complete 327 ill f20.4 wait for end-of-write (t wc , polling, or toggle bit)
44 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 49: f lash b ank w ord -p rogram f lowchart flash bank word-program start software data protect program flash bank command set word address load word data flash bank word-program complete 327 ill f21.3 wait for end of program (t bpf , data # polling, or toggle bit)
data sheet 16 megabit flashbank memory sst38vf166 45 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 50: e 2 b ank w ord -p rogram f lowchart e 2 bank word-program start software data protect program e 2 bank command set word address load word data e 2 bank word-program complete 327 ill f22.3 wait for end of program (t bpe , data # polling, or toggle bit)
46 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 51: e nd - of -w rite , e rase , or p rogram w ait o ptions f lowchart internal timer erase, program, or write operation initiated 327 ill f23.1 wait t wc , t bpe , t bpf , t sef , t lef , t bef , t see or t bee erase, program, or write completed toggle bit data# polling erase, program, or write operation initiated read a word from a bank, block, sector, or word selected read the same word again is dq6 the same? no no ye s erase, program, or write operation initiated read dq7 of the last address set (or any address within selected bank, block, sector for erase) erase, program, or write completed erase, program, or write completed is dq7 same as bit loaded?
data sheet 16 megabit flashbank memory sst38vf166 47 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 figure 52: c oncurrent o peration f lowchart 327 ill f24.1 load sdp command sequence concurrent operation flash program/erase or e 2 write initiated wait for end-of-write indication flash operation completed end concurrent operation read another bank end wait
48 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 sst38vf166 valid combinations SST38VF166-70-4C-EK example: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative t o confirm availability of valid combinations and to determine availability of new combinations. device speed suffix1 suffix2 sst38v f166 - xxx -x x -x x package modifier k = 48 balls package type e = tsop (12mm x 20mm) temperature range c = commercial = 0 c to +70 c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns vo ltag e v = 2.7-3.6v
data sheet 16 megabit flashbank memory sst38vf166 49 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 packaging diagrams 48-p in t hin s mall o utline p ackage (tsop) 12 mm x 20 mm sst p ackage c ode : ek 48.tsop-ek-ill.5 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 4. maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 12.20 11.80 .270 .170 1.05 0.95 . 50 bsc 0.15 0.05 18.50 18.30 20.20 19.80 0.70 0.50 pin # 1 identifier
50 data sheet 16 megabit flashbank memory sst38vf166 ?2001 silicon storage technology, inc. 327-3 2/01 s71065 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.ssti.com

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